Embodiments of the present invention relate to semiconductor process control, reliability and testing. More particularly, embodiments of the present invention provide a method of detecting shallow trench isolation corner thinning by electrical stress.
For reasons of cost improvement, increasing speed of operation, power consumption decreases and other well known reasons, the semiconductor industry is pushing the geometry of integrated circuits to ever smaller sizes A typical size of the smallest feature on a chip is, for example, 0.18 xcexcm. As semiconductors are designed for this and smaller geometries, the once dominant isolation technique known as LOCOS, Local-Oxidation of Silicon, is becoming less prominent, and a newer technique known as Shallow Trench Isolation, STI, is becoming the preferred method of isolation.
When compared to LOCOS, STI generally requires a much smaller area to isolate transistors while offering superior latch-up immunity, smaller channel width encroachment and better planarity. LOCOS is generally a very high temperature process, performed at temperatures of approximately 1,000 degrees C. STI generally is processed at significantly lower temperatures, typically around 500 degrees C. LOCOS commonly suffers from two well known characteristics known as bird""s beak and encroachment, which do not occur with STI. Further, by separating two active devices by a trench as with STI, the electrical field lines have to travel a longer distance and change direction twice, so they are considerably weakened. Therefore, trenches of sub-micrometer dimensions are adequate for isolation to prevent punch-through and latch-up phenomena Consequently, STI structures and processes allow for the required isolation at smaller semiconductor process geometries and with smaller structures than does LOCOS.
Unfortunately, STI is generally a more difficult process to control. To some extent, this results from the smaller size and thinner layers of the structures. As a result, process control, and the corollary quality inspections are of critical importance in an STI process.
The well known, industry-wide standard inspection method is to examine sections of a semiconductor wafer with a tunneling electron microscope, TEM, to measure the thickness of the various layers, for example, polysilicon, oxide, metalization, etc.
Unfortunately, such use of the TEM has many undesirable drawbacks. Because it is a destructive test, it can only be applied to a sample of a batch of wafers. Further, it is well known in the industry that process quality and defects vary across a single wafer. This is especially true as the industry moves toward larger wafer sizes, for example, 8 and 12 inch wafers. A TEM inspection can physically only be made at a few points in a wafer. It is also a time consuming process to section, prepare and inspect samples via TEM. As an unfortunate result, the quality of the STI generally can only be examined in a rather limited fashion at a few sample points on very few sample wafers. Consequently, it is difficult to gain a thorough understanding of the process, and it is commercially infeasible to test all wafers for process quality.
What is highly sought in the industry, then, is a fast, non-destructive method of testing semiconductors constructed with STI, particularly a method of measuring the oxide thickness.
A method and apparatus for testing semiconductors comprising shallow trench isolation (STI) edge structures are disclosed. An edge intensive shallow trench isolation structure is coupled to a voltage source and a current profile is recorded. A planar structure on the same wafer is coupled to a voltage source and a current profile is recorded. An electrical stress is applied to both structures. Additional current profiles of each structure are obtained after the electrical stress. A comparison of difference current profiles obtained for the two types of structures may indicate the presence and/or the extent of STI corner effects. More specifically, a value for a normalized gate current difference for an STI edge intensive structure greater than normalized gate current difference of a planar structure is indicative of an increased rate of electron trapping in STI corners, which may indicate that the STI corners are too thin. In this novel manner, STI corner thickness may be observed in a non-destructive, electrical test process, resulting in higher quality and greater reliability of semiconductors using STI processes.